International Electron Devices Meeting (IEDM) 2025

Imec will be present at this year’s IEDM with 21 contributions, of which 19 first-authored papers. These contributions cover innovations in advanced logic, memory, quantum computing, and bioelectronics. Highlights include breakthroughs in CFET scaling, low-temperature processing, spintronics, and silicon photonics. From spectral sensors and superconducting circuits to solid-state nanopores and AI-driven retrospectives on FETs, imec’s contributions reflect its leadership in pushing semiconductor boundaries and system-level co-optimization.

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Overview imec contributions

Monday, December 8, 2025

• 8-5 | Metasurface Cointegration with Colloidal Quantum Dot Photodiodes Enabling Facile Spectral Sensors, G. Kara et al.
• 10-1 | Selective Etch Process for Fab-compatible Top Contacts, Replacement Oxide and Interlayer Removal in 2D FETs, Q. Smets et al
• 10-6 | Towards a Low-Disorder pFET Gate Stack for Monolayer WSe2 Channels, D. Ngo et al.
• 2-2 | Hybrid Channel monolithic-CFET with Si (110) pMOS and (100) nMOS, A. Vandooren et al.
• 2-3 | 3.5T CFET Block-Level DTCO for Superior PPA in A7 Node by Split Power, hDR Cells, Optimized Pins and BEOL, J. Lin et al.
• 2-6 | Multi-node Scaling Potential of Monolithic CFET, S. Yang et al.
• 2-8 | Junction-engineered Scaled High-performance GAA Nanosheet FETs with Ultra-low Temperature (< 350 °C) SiGe:B Source/Drain, R. Sarkar et al.

Tuesday, December 9, 2025

• 15-1 | First Demonstration of Field Free Switching Perpendicular SOT-MRAM 4kb Array Using Z-Spin, M. G. Monteiro Jr et al.
• 15-3 | Advancements in NbTiN based circuits for Superconducting Digital Logic, A. Pokhrel et al.
• 15-5 | 300mm fabrication of silicon quantum dot spin qubits using 0.33NA EUV lithography, S. Beyne et al.
• 17-3 | Breaking Thermal Bottleneck in 3D HBM-on-GPU Integration via System-Technology Co-Optimization, Y. Chen et al.
• 23-4 | Nanosecond-scale Transient Defect Spectroscopy of Switching and Relaxation Dynamics in GeAsSe Ovonic Threshold Switching Devices, N. Saxena et al.
• EP | FETs at 100: Yesterday’s Sparks, Tomorrow’s Arcs -- Human Wisdom Meets AI Insight, with Serge Biesemans

Wednesday, December 10, 2025

• 33-5 | Towards SoCs Leveraging 200nm Wafer-to-Wafer Interconnection Pitch, J. De Vos et al.
• 33-7 | Demonstration of 16nm Pitch Two Metal Level Fully Self-Aligned Via Ru Interconnects, G. Delie et al.
• 40-1 | Novel Low Temperature SiO2 Formation Process by Oxygen and Hydrogen Radicals for Core and I/O RMG Stacks: Achieving the Ultimate NBTI Reliability with a Charge-Free IL, J. Franco et al.
• 40-3 | First Systematic Characterization of Floating Body Effects in GAA Nanosheet 3D DRAM Access Transistors, D. Garbin et al.
• 41-3 | Silicon Photonics Modulators and Photodetectors for Next-Generation CPO and Optical I/O (Invited), J. Van Campenhout et al.
• 43-4 | Fabrication of Solid-State Nanopores with EUV Lithography, A. R. Chaudhuri et al.
• 40-5 | Improving IGZO transistor PBTI reliability with hydrogen anneal achieving overdrive voltage of 1.2V for a lifetime of 5 years at 95°C, A. Chasin et al.
• 43-6 | Aligned Carbon Nanotube BioFETs: Toward High-Throughput Single-Molecule Sensing, L. Liu et al.