Imec at the 70th International Electron Devices Meeting (IEDM)

Imec will be present at this year’s IEDM with 22 contributions, of which 20 first-authored papers. These contributions cover innovations in logic and memory, such as a new CFET standard cell architecture and a novel 3D buffer memory. Imec also reports progress in advanced nanosheet and CFET device manufacturing, MRAM and IGZO devices, superconducting logic technologies, and system-technology co-optimization of network-on-chip routing through backside technologies and 3D integration. Demonstrations of InP chiplets integrated on an RF silicon interposer, and of short-wave IR optical sensors are highlighted.

On the eve of this conference, imec is organizing ITF@IEDM – Leading Tomorrow: Pioneering Innovations from Lab to Fab. Here you will get a glimpse of imec’s breakthroughs, that are an integral part of imec's semiconductor and systems scale-up roadmap, underlining our commitment to pushing the boundaries of technology. You can find the full program and register here.

Highlights

2-4 | Double-Row CFET: Design Technology Co-Optimization for Area Efficient A7 Technology Node, H. Kukner et al.
Complementary FET (CFET) device architecture with stacked n-/p-FETs promises power, performance, area scalability in the post-FinFET era. Among several options, the double-row CFET architecture leads to reduced process complexity in the middle-of-line, and gains in logic and SRAM area. Projections show ~40% area and ~12% power scaling potential

2-7 | Monolithic-CFET with Direct Backside Contact to Source/Drain and Backside Dielectric Isolation, A. Vandooren et al.
This work reports on demonstration of monolithic complementary field effect (CFET) transistors using direct backside (BS) contact (DBC) to source and drain (SD) of the bottom PMOS device. We compare two integration options to avoid shorts between DBC and gate and/or Si substrate relying either on the use of an offset spacer or on formation of bottom dielectric isolation from the backside (BS-BDI). Both integration options result in functional bottom (pFET) and top (nFET) CMOS devices on a common gate at 60 nm gate pitch.

9-1 | Hetero-Integration of InP Chiplets on a 300 mm RF Silicon Interposer for mm-wave Applications, S. Sinha et al.
Hetero-Integration of InP Chiplets on a 300 mm RF Silicon Interposer is reported with interposer line loss of 0.23-0.3 dB/mm, flip-chip interconnect loss of 0.1 dB both at 140 GHz. Hetero-integrated PA has16.3 dB small-signal gain, 116-148 GHz bandwidth, P1dB of 13-15 dBm and 15-28 % PAE.

19-6 | Magnetic immunity of STT-MRAM: external magnetic field orientation impact on writing reliability, N. Vander Meeren et al.
We experimentally investigate the writing reliability of STT-MRAM in the presence of magnetic fields oriented at different angles. It is established that external magnetic fields oriented non-parallel to the easy axis of the device significantly increase the write error rate for short pulse widths. These cases have been ignored in magnetic immunity testing thus far. More precisely, at 40mT, the write error rate is shown to deteriorate by over a factor of 10³ depending on the angle of the external field. Moreover, these results are corroborated by stochastic LLGS simulations.

42-1 | Achieving 1ppm write-error rate in SOT-MRAM with synthetic antiferromagnetic free layer, D. Nguyen et al.
We demonstrate functionality of a perpendicular SOT-MRAM with a synthetic antiferromagnetic-based free layer MTJ, reducing the write error rate to 10^-6 and maintaining BEOL compatibility at 400 ^oC. Micromagnetic simulations guide material selection, ensuring reliable device operation for experimental validation. These devices fabricated on 300 mm wafers advance technological integration.

31-3 | System technology co-optimization of cost-bandwidth tradeoffs in Network on Chip through 3D integration and backside signals, M. Brunion et al.
The routing of the NoC in many-core systems allocates floorplan resources, which are scaling slower through technology advancements than high-density logic in conventional 2D systems. In this paper we compare fine-grained disintegration of the NoC channel routing through 3D-die stacking and signals routed on wafer backside. Physical modelling using a A10 nanosheet technology suggests that extending the backside metal stack with 2 or 3 dedicated, bidirectional routing layers provides a cost effective scaling booster, and is preferable to heterogeneous 3D implementations. We estimate up to 20% lower cost over the 3D-stacking approach and 2D baseline at 3500 signals per channel-link.

34-2 | Unraveling BTI in IGZO devices: impact of device architecture, channel film deposition method and stoichiometry/phase, and device operating conditions, A. Chasin et al.
We study the impact of the device architecture, channel deposition method, stoichiometry and phase, and AC stress on the BTI of IGZO transistors. Two main conclusions are obtained. Firstly, reliability of IGZO based devices is strongly architecture dependent, and therefore reliability solutions are not universal. Secondly, top-gate devices are more severely impacted by the abnormal negative ΔVth, ascribed to a H-doping process, than back-gated counterparts. Two remedies for the negative ΔVth are identified: In-poor films and AC stress with duty-cycle<25% do not reveal sings of H-doping process within the experimental time window, promising for reliable product operation.

37-6 | Novel High Density 3D Buffer Memory Enabled by IGZO Channel Charge Coupled Device, R. Kishore et al.
We present a novel 3D Charge Coupled Device (CCD) with IGZO channel for high density block addressable buffer memory integrable in 3D NAND Flash string architecture. The concept is demonstrated using planar 4-phase CCD structure with 142-bits featuring efficient and fast charge transfer, long retention, large endurance, and multilevel capability.

39-3 | NbTiN based two-metal level semi-damascene interconnects, Josephson junctions and capacitors for Superconducting Digital Logic, A. Pokhrel et al.
Superconducting Digital (SCD) is a promising alternative to CMOS technology, enabling energy-efficient High-Performance Computing. We report the fabrication of three key devices for SCD: NbTiN BEOL interconnects, NbTiN/αSi/NbTiN Josephson junctions (JJs), and NbTiN/HZO/NbTiN Metal-Insulator-Metal (MIM) capacitors. Material characterization demonstrate high-quality devices with critical dimensions down to 50 nm. NbTiN interconnects have critical temperature >13K and high critical current density (Jc) >120 mΑ/µm2, JJs have Jc of 0.4 mΑ/µm2. MIM capacitors have high specific capacitance of ~28 fF/µm2 (k-value=30). Devices were fabricated using CMOS compatible processes below 420oC on 300mm wafers, bridging the gap from feasibility to industrial fabrication.

41-8 | Lead-Free Quantum Dot Photodiodes for Next Generation Short Wave Infrared Optical Sensors, W. Song et al.
Colloidal quantum dot sensors are disruptingimaging beyond the spectral limits of silicon. In this paper,we present imagers based on InAs QDs as alternative for 1stgeneration Pb-based stacks. New synthesis method yields 9nm QDs optimized for 1400 nm and solution-phase ligandexchange results in uniform 1-step coating. Initial EQE is17.4% at 1390 nm on glass and 5.8% EQE on silicon(detectivity of 7.4 × 109 Jones). Using metal-oxide transportlayers and >300 hour air-stability enable compatibility withfab manufacturing. These results are a starting point towardsthe 2nd generation quantum dot SWIR imagers.

Overview imec contributions

Monday, December 9, 2024

• 2-4 | Double-Row CFET: Design Technology Co-Optimization for Area Efficient A7 Technology Node, H. Kukner et al.
• 2-7 | Monolithic-CFET with Direct Backside Contact to Source/Drain and Backside Dielectric Isolation, A. Vandooren et al.
• 7-2 | Multiscale Thermal Impact of BSPDN: SoC Hotspot Challenges and Partial Mitigation, B. Vermeersch et al.
• 9-1 | Hetero-Integration of InP Chiplets on a 300 mm RF Silicon Interposer for mm-wave Applications, S. Sinha et al.

Tuesday, December 10, 2024

• 12-4 | High-performance Monolayer-2D Stacked Nanosheet FETs with high ION ~ 451 µA/µm and ION/IOFF > 109, F. Xi et al.
• 14-2 | Neuropixels probe: A 130nm/55nm CMOS-based integrated Multimodal Microsystems Technology Platform for large scale Brain Wide Recording, B. Dutta et al.
• 17-2 | Selector Only Memory: Exploring Atomic Mechanisms from First-Principles, S. Clima et al.
• 19-5 | Understanding the Variability in GeAsTe Ovonic Threshold Switching Devices, Z Hu (Liverpool John Moores University) et al. (co-authored by imec)
• 19-6 | Magnetic immunity of STT-MRAM: external magnetic field orientation impact on writing reliability, N. Vander Meeren et al.
• 24-2 | The critical role of 2D TMD interfacial layers for pFET performance, T. D. Ngo et al.

Wednesday, December 11, 2024

• 30-5 | Novel Design Strategy for High-Endurance (>1010) and Fast-Erase Oxide-Semiconductor Channel FeFET, Z. Chen et al.
• 31-3 | System technology co-optimization of cost-bandwidth tradeoffs in Network on Chip through 3D integration and backside signals, M. Brunion et al.
• 33-2 | Propelling Widespread GaN Electronics Adoption With Large Diameter and CMOS Fab Friendly GaN-on-QST® Manufacturing Platform, V. Odnoblyudov (QROMIS, Inc.) et al. (co-authored by imec)
• 34-1 | Low Thermal Budget Multi-Vth RMG solution with excellent TDDB and BTI Reliability by combining hydrogen radical IL treatment, n-dipole-first shifter and low-temperature HK PDA, J. Franco et al.
• 34-2 | Unraveling BTI in IGZO devices: impact of device architecture, channel film deposition method and stoichiometry/phase, and device operating conditions, A. Chasin et al.
• 37-5 | Improved Capacitive Memory Window for Non-destructive Read in HZO-based Ferroelectric Capacitors with Incorporation of Semiconducting IGZO, S. Mukherjee et al.
• 37-6 | Novel High Density 3D Buffer Memory Enabled by IGZO Channel Charge Coupled Device, R. Kishore et al.
• 39-3 | NbTiN based two-metal level semi-damascene interconnects, Josephson junctions and capacitors for Superconducting Digital Logic, A. Pokhrel et al.
• 39-5 | Nb Contacts for Thermally-stable High-performance Logic and Memory Peripheral Transistor, R. Sarkar et al.
• 39-6 | Direct extraction of contact and S/D epi access resistance components on 45nm Gate Pitch NS-based n-FET devices for the 2nm node, P. Eyben et al.
• 41-8 | Lead-Free Quantum Dot Photodiodes for Next Generation Short Wave Infrared Optical Sensors, W. Song et al.
• 42-1 | Achieving 1ppm write-error rate in SOT-MRAM with synthetic antiferromagnetic free layer, D. Nguyen et al.