International Electron Devices Meeting (IEDM) 2025

This year at the 71^st International Electron Devices Meeting, imec is present with 21 accepted papers, of which 19 first-authored papers and 1 invited paper. These contributions cover innovations in advanced logic, memory, quantum computing, imaging and bioelectronics. Highlights include breakthroughs in thermal bottleneck mitigation in 3D HBM-on-GPU architectures through cross-technology co-optimization (XTCO), wafer-scale fabrication of solid-state nanopores for molecular sensing, 2D-material based device technology advancements supporting the enablement of the future logic technology roadmap, integration of colloidal quantum dot photodiodes for compact, next-generation short-wave infrared imagers, scalability of monolithic CFET device architectures, upscaling Si MOS quantum dot spin qubit technology, advances in material science and fabrication methods for superconducting digital logic circuits.

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Highlights

Thermal bottleneck in 3D HBM-on-GPU architectures using a system-technology co-optimization approach

Imec will present the first thermal system-technology co-optimization study of 3D HBM-on-GPU, a promising compute architecture for next-gen AI applications. By combining technology and system-level mitigation strategies, peak GPU temperatures could be reduced from 140.7°C to 70.8°C under realistic AI training workloads – on par with current 2.5D integration options. The result demonstrates the strength of combining cross-layer optimization (i.e., co-optimizing the knobs at all the different abstraction layers) with broad technological expertise, a combination that is unique to imec.  

See paper:

• 17-3 | Breaking Thermal Bottleneck in 3D HBM-on-GPU Integration via System-Technology Co-Optimization, Y. Chen et al.

Solid-state nanopores using EUV lithography

Imec will present the first successful wafer-scale fabrication of solid-state nanopores using extreme ultraviolet (EUV) lithography. Solid-state nanopores are emerging as powerful tools for molecular sensing but haven't been commercialized yet. This proof of concept is a crucial step towards their cost-effective (mass) production.  

 See paper:

• 43-4 | Fabrication of Solid-State Nanopores with EUV Lithography, A.R. Chaudhuri, et al. 

Advances of 2D-material based device technology

Imec will present breakthrough performance of p-type FETs with monolayer WSe₂ channels, and improved fab-compatible modules for source/drain contact formation and gate stack integration. These results, achieved through collaborations with leading semiconductor manufacturers, mark a significant advance for 2D-material based technology, which is considered a promising long-term option for extending the logic technology roadmap. 

See papers:

• 10-1 | Selective Etch Process for Fab-compatible Top Contacts, Replacement Oxide and Interlayer Removal in 2D FETs, Q. Smets, et al.
• 10-6 | Towards a Low-Disorder pFET Gate Stack for Monolayer WSe₂ Channels, D. Ngo, et al.

Colloidal quantum dot photodiodes (QDPDs) on metasurfaces developed on 300mm CMOS wafers

Imec will demonstrate the integration of colloidal quantum dot photodiodes (QDPDs) on metasurfaces developed on its 300 mm CMOS pilot line. This pioneering approach enables a scalable platform for the development of compact, miniaturized shortwave infrared (SWIR) spectral sensors, setting a new standard for cost-effective and high-resolution spectral imaging solutions. 

See paper: 

• 8-5 | Metasurface Cointegration with Colloidal Quantum Dot Photodiodes Enabling Facile Spectral Sensors, G. Kara, et al. 

Scalability of monolithic CFET

In recent years, significant progress has been made in developing process flows for monolithic CFET (mCFET) device architectures.  However, the semiconductor industry will only be willing to adopt this disruptive transistor architecture if it can be used across successive technology nodes. Imec will present a DTCO study to identify the performance boosters that are needed to support aggressive area scaling of mCFET device architectures for A7, A5 and A3 logic nodes. For the A3 node, hybrid channel orientations for n and pMOS transistors will be needed. Imec will also experimentally demonstrate the key process module that enables the integration of heterogeneous channels in a mCFET: the embedded middle dielectric isolation.

See papers:

• 2-2 | Hybrid Channel monolithic-CFET with Si (110) pMOS and (100) nMOS, A. Vandooren, et al.
• 2-6 | Multi-node Scaling Potential of Monolithic CFET, S. Yang, et al.

Research update - Si MOS quantum dot spin qubits

In its quest to develop useful quantum computers, the quantum community spreads its efforts across two areas: developing ‘better’ qubits and enabling ‘more’ qubits. Si quantum dot spin qubit technology provides an attractive platform that can address both challenges.  Imec earlier reproducibly demonstrated high-fidelity spin qubit operations – a prerequisite for large-scale quantum computing – on quantum dot structures fabricated with imec’s optimized 300mm fab-compatible process flow. Two key innovations now mark another leap forward in the race to scale up: (1) the use of EUV lithography to enable full 300mm wafer printability with excellent reproducibility, and (2) the transition to scalable quantum dot device architectures to address the wiring bottleneck. 

See paper:

• 15-5 | 300mm fabrication of silicon quantum dot spin qubits using 0.33NA EUV lithography, S. Beyne et al.

Research update – Superconducting Digital Logic

Superconducting (SC) electronics have emerged as a promising platform for high-speed, energy-efficient computing and quantum information processing. Imec will present their work, centered on NbTiN-based SC digital technology, that shows recent advances in material science and fabrication methods leading to significant improvements in performance, scalability and vertical integration. Researchers specifically report on the fabrication and characterization of key components, including Josephson junctions (JJs), flux trapping structures and SC interconnects. Together, these efforts represent critical steps towards realizing practical, complex, dense and large-scale SC integrated circuits.

See paper:

• 15-3 | Advancements in NbTiN based circuits for Superconducting Digital Logic, A. Pokhrel, et al. 

Invited paper – SiPho modulators and photodetectors

Joris Van Campenhout, fellow at imec, is invited to present a paper on silicon photonics modulators and photodetectors for next-generation co-packaged optics and optical I/O. In this presentation, he will review the recent performance of high-speed, high-efficiency electro-optical modulators and photo-detectors, targeting next-generation co-packaged optics (CPO) operating at 400G/lane and future Optical I/O (OIO), employing a “wide-and-slow” parallel interface. The presentation focuses on compact devices, including Si ring and disk modulators, as well as electro-absorption modulators implemented in Ge(Si) or through heterogeneous InP-on-Si integration. Finally, a performance overview will be provided of recently developed Si-integrated Ge photodetectors, capable of supporting both next-generation CPO and Optical I/O.

See paper and more:

• 41-3 | Silicon Photonics Modulators and Photodetectors for Next-Generation CPO and Optical I/O (Invited), J. Van Campenhout.
• Imec debuts a beyond-110GHz C-band GeSi electro-absorption modulator (EAM) on its 300mm silicon photonics platform

Evening panel – FETs at 100

Serge Biesemans, VP R&D at imec, will partake in the evening panel discussion alongside other industry experts representing Samsung Electronics, TSMC & Stanford University, UC Berkeley and AMD. In this panel discussion, panelists will reflect on and celebrate through thought-provoking discussion and debate the extraordinary journey of FETs through the last 100 years and to anticipate the exciting developments that lie ahead. 

Go to panel details: 

• EP | FETs at 100: Yesterday’s Sparks, Tomorrow’s Arcs -- Human Wisdom Meets AI Insight

Overview imec contributions

Monday, December 8, 2025

• 2-2 | Hybrid Channel monolithic-CFET with Si (110) pMOS and (100) nMOS, A. Vandooren et al.
• 2-3 | 3.5T CFET Block-Level DTCO for Superior PPA in A7 Node by Split Power, hDR Cells, Optimized Pins and BEOL, J. Lin et al.
• 2-6 | Multi-node Scaling Potential of Monolithic CFET, S. Yang et al.
• 2-8 | Junction-engineered Scaled High-performance GAA Nanosheet FETs with Ultra-low Temperature (< 350 °C) SiGe:B Source/Drain, R. Sarkar et al.
• 8-5 | Metasurface Cointegration with Colloidal Quantum Dot Photodiodes Enabling Facile Spectral Sensors, G. Kara et al.
• 10-1 | Selective Etch Process for Fab-compatible Top Contacts, Replacement Oxide and Interlayer Removal in 2D FETs, Q. Smets et al
• 10-6 | Towards a Low-Disorder pFET Gate Stack for Monolayer WSe2 Channels, D. Ngo et al.

Tuesday, December 9, 2025

• 15-1 | First Demonstration of Field Free Switching Perpendicular SOT-MRAM 4kb Array Using Z-Spin, M. G. Monteiro Jr et al.
• 15-3 | Advancements in NbTiN based circuits for Superconducting Digital Logic, A. Pokhrel et al.
• 15-5 | 300mm fabrication of silicon quantum dot spin qubits using 0.33NA EUV lithography, S. Beyne et al.
• 17-3 | Breaking Thermal Bottleneck in 3D HBM-on-GPU Integration via System-Technology Co-Optimization, Y. Chen et al.
• 23-4 | Nanosecond-scale Transient Defect Spectroscopy of Switching and Relaxation Dynamics in GeAsSe Ovonic Threshold Switching Devices, N. Saxena et al.
• EP | FETs at 100: Yesterday’s Sparks, Tomorrow’s Arcs -- Human Wisdom Meets AI Insight, with Serge Biesemans

Wednesday, December 10, 2025

• 33-5 | Towards SoCs Leveraging 200nm Wafer-to-Wafer Interconnection Pitch, J. De Vos et al.
• 33-7 | Demonstration of 16nm Pitch Two Metal Level Fully Self-Aligned Via Ru Interconnects, G. Delie et al.
• 40-1 | Novel Low Temperature SiO2 Formation Process by Oxygen and Hydrogen Radicals for Core and I/O RMG Stacks: Achieving the Ultimate NBTI Reliability with a Charge-Free IL, J. Franco et al.
• 40-3 | First Systematic Characterization of Floating Body Effects in GAA Nanosheet 3D DRAM Access Transistors, D. Garbin et al.
• 40-5 | Improving IGZO transistor PBTI reliability with hydrogen anneal achieving overdrive voltage of 1.2V for a lifetime of 5 years at 95°C, A. Chasin et al.
• 41-3 | Silicon Photonics Modulators and Photodetectors for Next-Generation CPO and Optical I/O (Invited), J. Van Campenhout et al.
• 43-4 | Fabrication of Solid-State Nanopores with EUV Lithography, A. R. Chaudhuri et al.
• 43-6 | Aligned Carbon Nanotube BioFETs: Toward High-Throughput Single-Molecule Sensing, L. Liu et al.