(if the hardware allows it)

Validating sustainability strategies with real-fab solutions

Advances in wafer-to-wafer hybrid bonding and backside technologies take CMOS 2.0 from concept to reality, offering more options for compute system scaling

Improved contact resistance and RF output key toward mobile-compatible E-mode GaN-on-Si transistors

High-speed DAC paves the way for faster and more energy-efficient optical and electrical links in data centers

Improved manufacturability and performance compared to the earlier inner wall forksheet

A programmable solution for higher-speed wireless communication networks and low-cost microwave sensing

A cost-effective approach to patterning the first local interconnect metal layer of A7 and beyond logic nodes 

Flexible integration of digital, analog, RF-to-sub-THz CMOS and III/V chiplets on a single carrier paves the way for high-performance RF and mixed-signal applications 

Imec enables the ‘curvilinear’ manufacturing ecosystem – from design over OPC and mask to wafer.

Imec will work with multiple MIT labs to explore groundbreaking diagnostic devices and improve quality of life