Area-selective deposition (ASD): a bottom-up fabrication paradigm to enable nanoscale structures

Over the last six decades, the use of electronic devices has become prominent in our society. The downscaling of the single components (e.g., transistors) and the introduction of three-dimensional (3D) stacked integrated circuit designs have made every-day-use objects such as laptops and smartphones possible.

The shrinking of feature sizes has been largely possible because of the continuous innovation in lithography. However, this downscaling is also accompanied by an increased complexity and cost factor in device fabrication. The overlay requirement typically has been ¼ of the minimum printable size (also referred to as critical dimension,

CD). However, to successfully fabricate 7 or 5 nm technology nodes, the overlay must

be between 1/6 and 1/10 of the CD. Selective processing techniques, such as area-selective ALD, can intrinsically enable perfect overlap between the features present at the different levels of the device, or can be used to mitigate the alignment issues and therefore keep performance and yield as high as possible.

ASD holds great potential to complement traditional patterning for the fabrication of nano-electronic devices. In ASD, material is deposited only where needed according to a predefined pattern, with no deposition on the rest of the surface. ASD is a sustainable and cost-effective approach that allows reducing chemical and energy consumption as compared to traditional top-down patterning. Nevertheless, industrial applications of ASD are currently limited, because only few materials can be deposited with high selectivity. We therefore investigate the growth and nucleation mechanisms of Atomic Layer Deposition and Chemical Vapor Deposition and apply the insight to design novel ASD processes.