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Design and System Technology Co‑Optimization Framework for Next‑Generation 3D High-Bandwidth Memory
Leuven | Just now
Bridging device technology and system design to shape the next generation of 3D high-bandwidth memory
As 3D-stacked high-bandwidth memory (HBM) technologies become critical for modern AI and HPC systems, understanding system‑level implications of device, technology, and architectural choices is essential. This internship focuses on developing a Design‑Technology Co‑Optimization (DTCO) and System‑Technology Co‑Optimization (STCO) evaluation framework for next‑generation 3D HBM solutions. The framework will integrate models spanning bit‑cell/device characteristics, array organization, 3D stacking, and multi‑channel memory subsystem behavior. The student will analyze how technology choices propagate to system‑level performance, bandwidth scaling, energy efficiency, and area constraints. The resulting framework will enable early‑stage trade‑off studies to guide future memory roadmaps.
Skills to stand out:
- Solid understanding of memory subsystem
- Familiarity with different bit cell concepts
- Strong programming skills in C++ or Python
- Experience with performance modelling techniques
- Exposure to system-level simulation tools or benchmarking frameworks is a plus (Ramulator, DRAMSys, DRAMSim, Gem5, …)
Type of internship: Master internship
Duration: 6-9 months
Required educational background: Computer Science, Electrotechnics/Electrical Engineering
Supervising scientist(s): For further information or for application, please contact Khakim Akhunov (Khakim.Akhunov@imec.be)
The reference code for this position is 2026-INT-043. Mention this reference code in your application.
Imec allowance will be provided for students studying at a non-Belgian university.
Applications should include the following information:
- resume
- motivation
- current study
Incomplete applications will not be considered.