Design Technology Co-Optimization for Advanced Technologies

Advanced technologies are pushing the limits of both design and technology capabilities, resulting in complex device architectures to achieve ever better power, performance and area (PPA) trade-offs. Precise modeling, where parasitic effects are meticulously addressed, is key for these advanced technologies. Using accurate parasitic extraction (PEX), a PEX RC netlist is created for each standard cell / design. This requires a deep understanding of both design and technology aspects.

In this internship, you will:

• Dive deeply into one or more advanced technologies, understanding key design and technology aspects, and comprehend the device architecture.
• Define the technology stack in collaboration with process and device experts.
• Design layouts for the considered technologies. 
• Transform these layouts into 3D structures for PEX, using inhouse software.
• Run benchmarks with the extracted PEX netlists and analyze the results.

During this internship you will be part of a multidisciplinary team, interacting with specialists in device physics, process integration and digital and/or memory design.

By joining imec for this internship, you will become part of a world-leading research institute in nanoelectronics. At imec, we foster a collaborative culture that thrives on innovation and continuous learning. You will work within a diverse and global team of experts, where your contributions will have real-world impact. Imec supports your professional and personal development, preparing you for a future at the cutting edge of technology.

Background: Applicants should have a background in nanotechnology, electrical engineering or related fields, with a strong cross-disciplinary interest.