Design-Technology Co-Optimization (DTCO) benchmarking for IGZO in advanced technologies

IGZO transistors have demonstrated potential in different applications, such as embedded DRAM or power switches. As each application demands distinct specifications, exploring a variety of technology options is crucial. A technology optimization exercise, where the parasitics are meticulously studied, will enhance each one of these applications.

In this internship, you will:

• Explore various IGZO technology options in collaboration with integration and application engineers.
• Analyze one or more application for IGZO and identify the distinct features in the technology architecture with significant impact for this application.
• Model the parasitics of the defined architectures with state-of-the-art simulation tools.
• Benchmark different IGZO technology options for one or more applications.

During this internship you will be part of a multidisciplinary team, interacting with specialists in device physics, process integration and digital design.

By joining imec for this internship, you will become part of a world-leading research institute in nanoelectronics. At imec, we foster a collaborative culture that thrives on innovation and continuous learning. You will work within a diverse and global team of experts, where your contributions will have real-world impact. Imec supports your professional and personal development, preparing you for a future at the cutting edge of technology.

Background: Applicants should have a background in nanotechnology, electrical engineering, physics, or related fields, with a strong cross-disciplinary interest.

Type of Project: Internship

Master's degree: Master of Engineering Science; Master of Engineering Technology

Duration: min. 3 months

For more information or application, please contact the supervising scientist Lynn Verschueren (lynn.verschueren@imec.be).

Imec allowance will be provided.