Imec demonstrates the first 3D implementation of a charge coupled device for AI memory applications

LEUVEN (Belgium), MAY 12, 2026— This week, at the 2026 IEEE International Memory Workshop (IMW), imec, a world-leading research and innovation hub in advanced semiconductor technologies, presents a 3D implementation of a CCD memory device with IGZO channel – a world first. The functional 3D CCD device consists of vertical memory holes drilled through a stack of 3 word-lines, serving as phase gates. Transfer of charges (that make up the bits) across the gates could be demonstrated at >4MHz transfer speed. The feasibility of processing the CCD device in a 3D NAND Flash architecture ensures cost-effective fabrication and bit densities surpassing the DRAM limit. This makes the block-addressable 3D CCD device an attractive compute express link (CXL® ) type-3 buffer memory for AI use cases – designed to feed multiple processors with large blocks of data through a high-bandwidth CXL®  switch.

AI’s insatiable hunger for memory is putting significant pressure on DRAM-based memory technology, which increasingly struggles to maintain the cost-per-bit scaling trendline. The memory industry therefore explores alternative, more cost-effective memory solutions that can complement DRAM and DRAM-based high bandwidth memory (HBM) for AI-specific workloads. In parallel, new memory interfaces have emerged that allow for more efficient use of the main memory resources compared to traditional double data rate (DDR) buses. One of these is CXL®, a memory protocol designed to make large pools of memory available to multiple processors through a high-bandwidth CXL® switch. These so-called CXL® type-3 buffer memories have different specifications than DRAM, offering an excellent opportunity for the introduction of new memory technology.

In 2024, imec conceptually introduced the 3D CCD with an IGZO channel – offering promising prospects to be used as a CXL® type-3 buffer memory – and demonstrated memory operation on a 2D proof-of-concept. Maarten Rosmeulen, Program Director Storage Memory at imec: “The potential of this CCD device to be used as a buffer memory lies in its ability to be integrated in a 3D NAND Flash string architecture – the most cost-effective way to achieve a scalable, high bit density estimated to go far beyond the DRAM limit. We now show for the first time a functional 3D implementation with a 3-word-line structure, achieving vertical IGZO channels at dimensions comparable with what can be achieved for 3D NAND (i.e., 80-120nm diameter memory holes).” 

In the 3D device, the CCD registers – or strings – are integrated into vertically aligned plugs, which are drilled through the 3-word-line stack using a 3D NAND-inspired punch-and-plug process. The horizontal word-lines act as the gates and determine a series of bits in each string. These bits are based on charges, which can be serially transferred and stored across the gates using a pulsed voltage scheme.

“We achieve reliable charge transfer along the vertical IGZO channel at speeds exceeding 4MHz,” adds Maarten Rosmeulen. “The number of charges transferred per cycle was measured to be a few thousand, which is sufficient for one bit or even multibit storage in real memory applications. Unlike byte-addressable DRAM, our 3D CCD device is designed to provide block-level data access, which is better suited to modern AI workloads. These results, in combination with unlimited endurance, long data retention (ensured by the IGZO channel material), and low-voltage operation (due to the charge-based nature of the memory operation) bring the 3D CCD technology a step closer to buffer memory implementations. In ongoing work, we focus on expanding the number of word-lines and optimizing the readout stage of our 3D CCD buffer memory. We are now ready to take our 3D CCD device technology to the next level with industry partners and fully unlock its potential for AI memory applications.”