Current in plane tunneling benchamarking of superconducting Josephson junctions

Superconducting processors leveraging Josephson junctions (JJs) represent a powerful alternative to traditional CMOS‑based computing, offering the potential for exceptionally high speed and dramatically reduced energy consumption. Despite this promise, conventional niobium (Nb)‑based JJs encounter significant scaling challenges, such as limited critical current densities (J₍c₎ < 1 mA/µm²), device dimensions that typically cannot shrink below ~250 nm, inherently low kinetic inductance, and a modest thermal budget of around 200 °C. These limitations restrict their integration into CMOS‑compatible fabrication flows and impede the realization of dense, low‑loss superconducting circuits.

Recent advances provide a path forward. By using NbTiN/α‑Si/NbTiN junction stacks fabricated through a semi‑damascene process on 300 mm wafers, it is now possible to achieve critical current densities of approximately 2–3 mA/µm² and junction dimensions as small as 210 nm. These improvements significantly enhance scalability and enable the creation of more compact, efficient superconducting circuit architectures.

The aim of this work is to establish a clear relationship between CIPT‑extracted barrier properties on blanket JJ structures and the electrical behavior of fully fabricated junctions. By tracking how the resistance–area (RA) product evolves from blanket measurements to device‑level results, the project will uncover which fabrication steps most strongly influence junction performance. This comparison will help identify process‑sensitive stages that introduce variability—or, alternatively, demonstrate that the junctions remain robust and consistent throughout the entire fabrication flow.