Leuven | More than two weeks ago
“Optimizing Interconnects and Bitcells for Next-Gen 3D Embedded Cache Systems: Powering the Future of High-Density, Energy-Efficient Memory”
Over the decades, CMOS technology has enabled aggressive scaling of computing systems, primarily in an inward direction, resulting in increasingly smaller systems. However, as we progress, this inward scaling yields diminishing returns. Embedded caches based solely on SRAMs do not scale inwardly, occupying a growing area relative to the size of logic cores/multicores. As logic continues to shrink, the number of cores on a system has multiplied in recent years, necessitating larger amounts of embedded memory. How can we power or clock such embedded systems in the most energy-efficient way?
In addition to geometric constraints, state-of-the-art system functionality is increasingly driven by data-intensive applications like AI and ML, which demand higher memory capacities and advanced memory management schemes both within and beyond the chip. Edge devices, on the other hand, prioritize energy efficiency to extend battery life. Key limiting factors such as system yield, testing, dynamic and static power, data integrity, and variability hinder continued scaling at the current level. However, due to these growing demands, system expansion is still necessary, primarily occurring in an outward direction.
One decisive technological direction is the 3D integration of heterogeneous technologies, sometimes referred to as 5.5D integration. However, larger, deeper, denser embedded caches and the data movement to off-chip 2.5D memory systems entail issues primarily related to interconnects such as power, clock, and signal, which must be solved to achieve higher energy efficiency. Our approach needs to focus primarily on interconnect issues rather than device issues.
The general research domain of this work is the integration of power, clock, and signal delivery to 3D embedded cache memories, building upon the existing SRAM and mixed-signal knowledge base. The key outputs of this research work are:
Required background: Electrical Engineering
Type of work: 50% mixed signal circuit design, 20% modeling, 20% literature survey and 10% publication.
Supervisor: Wim Dehaene
Daily advisor: Prashant Dubey
The reference code for this position is 2025-069. Mention this reference code on your application form.