/Low dimensional material transistors for in-memory computation

Low dimensional material transistors for in-memory computation

Leuven | More than two weeks ago

Scaled transistor technology by combining low dimensional materials and ferroelectric dielectrics for next generation in-memory computing.

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Problem Statement:

2D materials are considered as potential candidates for replacing Si at advanced technology nodes, while Ferro-FETs show promise in computation-in-memory application. Conventional Ferro-FETs with Si channel suffer from natural SiO₂ layer formed at Si surface. By integrating ferroelectric material on 2D channel, Ferro-FETs with high density and large operating window can be achieved. Due to the lack of surface bonds, it is hard to deposition high quality ALD oxide on 2D material. The candidate will investigate the 2D – Ferro interface, integrate and characterize scaled Ferro-FETs and explore the potential application in in-memory computing.

IMEC has established device integration platform in 2D FETs as well as Ferro-FETs. This topic will explore the new frontier by combining 2D materials and ferroelectricity, extending the current 2D FETs scaling activity to More than Moore regime. This topic will lead to the application of 2D materials in in-memory computing.

Background:

The 2D team at IMEC has been leading the industrial research in EOT scaling of 2D materials [1]. Recently, TSMC reported scaled gatestack of ~2.5nm thickness with higher-K oxide [2]. The nucleation AlOx layer is formed by “nanofog” technology, similar to IMEC’s TMA-soak technology. TSMC further demonstrated the ferroelectricity of their scaled 2D FETs and its potential application as eNVM [3]. Due to the difficulty of top-gate oxide deposition on 2D, other reports focus on bottom-gate stack [4]. In general, top-gate Ferro-FET based on 2D material is an emerging research field with limited literature report.

References:

1. Wu, Xiangyu, et al. "Dual gate synthetic MoS2 MOSFETs with 4.56 µF/cm2 channel capacitance, 320µS/µm Gm and 420 µA/µm Id at 1V Vd/100nm Lg." 2021 IEEE International Electron Devices Meeting (IEDM). IEEE, 2021.

2. Lee, Tsung-En, et al. "Nearly Ideal Subthreshold Swing in Monolayer MoS₂ Top-Gate nFETs with Scaled EOT of 1 nm." 2022 International Electron Devices Meeting (IEDM). IEEE, 2022.

4. Lee, Tsung-En, et al. "High-Endurance MoS2 FeFET with Operating Voltage Fess Than IV for eNVM in Scaled CMOS Technologies." 2023 International Electron Devices Meeting (IEDM). IEEE, 2023.

5. Li, Lingqi, et al. "Physical reservoirs based on MoS2–HZO integrated ferroelectric field-effect transistors for reservoir computing systems." Nanoscale Horizons 9.5 (2024): 752-763.

Required background: Semiconductor device, nanoelectronics

Type of work: 70% experimental, 20% modeling/simulation, 10% literature

Supervisor: Michel Houssa

Daily advisor: Xiangyu Wu

The reference code for this position is 2025-060. Mention this reference code on your application form.

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