Standard cell pin design for block-level optimization in advanced CMOS nodes

Introduction & context

Imec performs exploratory research on the near-future CMOS technologies nodes. In the Physical Design Research (PDR) team, we focus on the implications of future CMOS device architectures (e.g. nanosheet, CFET, 2D FET, etc.) at the library- and block-level (e.g. processor, NoC, 3D). We do pathfinding for future technology enablers by Design Technology Co-Optimization (DTCO) and System Technology Co-Optimization (STCO) cycles.
Advancing along the CMOS scaling roadmap from FinFET to nanosheet and to CFET device architectures, introduces several changes on standard cell library design. As Back-end-of-Line (BEOL) metal line dimensions downscale to the deca-nanometer range, the pin shapes and arrangements of standard cells can highly influence the interconnect resistance/capacitance and routing quality of the final design. 
In this study, the student will evaluate the QoR (quality of results) impact of standard cell pin shapes and their distributions at the block-level Place and Route (PnR) experiments for a processor core. 

Your main responsibilities

In this internship project:

• The student will begin to design different versions of a given standard cell library for varying pin shapes and their distributions. Layout Exchange Format (.lef) files and Liberty (.lib) timing and power models will be characterized for each standard cell library.
• Next, block-level physical design experiments will be performed for each library version.
• Finally, the design routability (congestion, net completion distribution, wirelength distribution, etc.), performance and area results from physically implemented designs will be extracted and evaluated.

Competences expected

• Motivated, interested, analytical thinking,  
• Team player with effective communication skills,
• Master course-level knowledge on standard cells, digital design flow, synthesis, static timing analysis, place and route,
• Familiarity with Linux commands, 
• Shell, Tcl and Python scripting languages are a plus.

Further Reading

Entering the nanosheet transistor era
Imec puts complementary FET (CFET) on the logic technology roadmap
Enabling Sub-5nm CMOS Technology Scaling Thinner and Taller!
Design enablement of CFET devices for sub-2nm CMOS nodes

Type of Project: Internship

Master's degree: Master of Science; Master of Engineering Science; Master of Engineering Technology 

Master program: Electrotechnics/Electrical Engineering; Nanoscience & Nanotechnology 

Duration: 3-4 months 

For more information or application, please contact Halil Kuekner (halil.kukner@imec.be)

Imec allowance will be provided for students studying at a non-Belgian university.