Article ESD protection
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Longread

Towards efficient ESD protection strategies for advanced 3D systems-on-chip

Guidelines for protecting the internal I/O interfaces from electrostatic discharge during die or wafer bonding steps

Summary

The continuous scaling of interconnect densities in 2.5D/3D technologies leaves little room for implementing ESD protection circuits at the internal I/O interfaces.

This forces industry to invest more heavily in ESD prevention during die-to-die and die-to-wafer bonding steps, and to avoid over-design of the ESD protection circuits.

Doing that in the most efficient way requires a more fundamental understanding of the ESD events that happen at the internal I/O interfaces.

This article presents useful insights, translated into practical guidelines and research directions for circuit designers and bonding tool suppliers.