ADPLL
Use imec’s compact, ultra-low-power all-digital phase-locked loop to optimize your next-generation IoT radio.
The Internet of things (IoT) is transforming into the Internet of invisible things. We’re increasingly encircled by wirelessly connected devices that are hidden in our environment, such as:
- wireless microcontrollers and sensors for consumer, health or industrial automation applications
- hearing aids and other audio applications
- medical wearables – even ingestibles or implantables
The components of these tiny embedded systems are under pressure to shrink their size. And – because of small battery size and limited recharging options – their power budget. All while enabling new features such as wireless position measurement (micro-location) and passive sensing.
One key component of any wireless transceiver is the phase-locked loop (PLL), required for generating RF frequencies and derived clocks. It’s vital that this PLL can keep up with the power and area demands of future ultra-low-power generations of IoT systems in advanced CMOS process nodes. For example: novel transmitter architectures such as digital polar transmitters. That’s why imec has built up a leading knowhow of all-digital phase-locked loops (ADPLL).
The value of all-digital phase-locked loops
Why is the ADPLL such a crucial component for small and low-power systems? Consider that analog PLLs are one of the major power consumers in a radio IC and can take up 30% of its area. Switching to digital efficiently counters these drawbacks. And has the added benefits of better control and testability, and improved scaling to advanced CMOS nodes.
Until recently, digital PLLs lagged behind in terms of performance. Thanks to its multidisciplinary IC expertise, imec develops ADPLLs that not only excel in low power consumption (e.g. <0.67mW, generation 3 design) and small footprint (e.g., <0.2 mm² in 40nm CMOS, generation 3 design). They also exhibit excellent performance, such as low spurious emissions (spurs) by using innovative spur suppression techniques and sub-1ps jitter.
This outstanding performance is enabled by several innovations. Examples are extensive built-in self-calibration and advanced power-efficient spur mitigation. Digital phase unwrap increases robustness against frequency pulling/pushing effects. Moreover, the ADPLL implements dynamic-element-matching (DEM) and reset and retime techniques. This further improves the linearity of the digital-to-time converter (DTC), .
Furthermore, injection-locked ring-oscillator(RO)-based ADPLLs eliminate the need for on-chip inductors. This allows for highly area-efficient implementations in advanced process nodes.
Evaluation PCB for imec’s ADPLL.
Multiple generations
Imec uses its ADPLL as a valuable component in its radio technologies such as ultra-wide band (UWB) and Bluetooth Low Energy. These also enable next-generation phase-based distance measurement.
Imec ADPLLs support a range of applications and associated frequency ranges, from sub-GHz, over 2.4GHz (e.g., BLE/Wi-Fi) to multi-GHz (e.g. 3-10GHz UWB). They achieve ultra-low power consumption in the (sub-)milliwatt range. All without sacrificing (sub-)ps jitter performance (exact numbers depend on the targeted applications and implementations).
They have been silicon-proven in different process nodes, including 40nm, 28nm and 22nm. Also, imec supports industrial partners for custom ADPLL designs/derivatives for custom target specifications and other process nodes.
Test, model and license imec’s all-digital phase-locked loop
Are you interested in using imec’s ultra-low-power ADPLL in your radio device? Apart from taking a license on our IP, you can evaluate your application using our test ICs and comprehensive Python model to make bit- and cycle-accurate simulations.
