Linking metrology needs to the evolving logic technology roadmap
Until around 2005, the semiconductor industry advanced along an almost predictable path. Moore’s Law guided transistor density scaling, while Dennard scaling ensured that the power density remained constant. And all this happened at a minimal increase in cost. But since the mid-2000s, deviations from that path urged industry to gradually introduce new materials, more advanced lithography and patterning technologies, and novel device architectures. Looking ahead, we must break new ground to keep Moore’s Law going, driven by the explosive growth of AI and its diversifying needs. Next to dimensional scaling (xy scaling), full system stack co-optimization is the way forward, with 3D integration (z scaling) as one of the enabling technologies.
The increase in device complexity along with progress in dimensional scaling and the rise of 3D integration technologies bring about evolving needs for metrology and inspection. The role of these technologies in semiconductor manufacturing cannot be overstated: they ensure yield, performance, and reliability by controlling the manufacturing processes. Along the way, new metrology techniques have emerged – many of them pioneered by imec and its partners in metrology – to complement the technologies of the early days.
In this article, imec’s metrology experts take you on a journey through 40 years of in-fab metrology and inspection – linked to four distinct periods in the logic scaling roadmap – and conclude with imec’s view on the future roadmap. The authors gave a keynote presentation on this topic at the 2026 Metrology, Inspection and Process Control conference (a sub-conference of SPIE Advanced Lithography and Patterning), on the occasion of the conference’s 40th birthday [1]. The starting point of our journey – 1986 – is also the year in which metrology techniques like atomic force microscopy (AFM) and broadband plasma (BBP) were first applied. These are now an integral part of state-of-the-art semiconductor manufacturing.
Figure 1 – A view on imec’s logic scaling roadmap since 1986, linked to notable innovations in lithography and device technologies (as presented at 2026 SPIE AL+P [1]).
Overall drivers of in-fab metrology and inspection: accuracy, detectability, precision, throughput, cost, and sustainability
In-fab semiconductor metrology and inspection technologies support semiconductor manufacturing steps during processing in the fab. They are used for either process verification – to check whether a process meets design specs – or process control. During the latter, a product sample is processed, relevant properties are measured, and the process is adjusted to bring the next processed sample closer to its specification.
When developing new techniques for in-fab metrology and inspection, general criteria must be considered. Accuracy is the main requirement for metrology tool development, which focuses on measuring and quantifying dimensions – such as critical dimensions (CDs) of patterned structures. Different criteria apply to inspection, aimed at detecting a wide variety of defect types on a wafer at multiple process stages. Here, detectability of defects at the wafer scale is essential, without the need for measuring dimensions. For both metrology and inspection, operation in the fab additionally translates into specs for precision and throughput, while meeting cost and sustainability criteria.
The golden age of happy scaling: optical metrology dominates, first e-beam and scatterometry tools enter the stage
The timespan between 1986 and 2005 is part of the so-called happy scaling era: the semiconductor industry advanced merely by the dimensional scaling of chip components, supported by KrF-based lithography systems that operate using light at a wavelength of 248nm during exposure in the scanner.
The metrology and inspection landscape was dominated by optical tools such as optical microscopes and ellipsometers, using light sources to interact with the structures being measured. Optical tools were deployed for measuring linewidth, layer thickness, overlay, and for performing wafer inspection. Initially, most of the work was done manually and with a small number of product samples, limiting the use of metrology and inspection to process verification.
When dimensions became increasingly smaller and the logic roadmap approached the 130nm technology node, e-beam-based techniques were gradually being introduced to answer more stringent resolution requirements: CD scanning electron microscopy (CD-SEM) for measuring line widths, review SEM for defect ‘review’ and classification, and inspection SEM for wafer-level defect inspection.
Dimensional scaling also reduced the budget available for overlay between successively patterned layers, for example, between two metal layers in the back-end-of-line. Fortunately, evolutions in metrology techniques throughout the 1990’s gradually brought more automation and sampling, and higher accuracy. This allowed the semiconductor industry to start using overlay measurements for controlling and correcting any misplacements between successive layers.
Toward the end of the happy scaling era, scatterometry was introduced, a new promising diffraction-based optical metrology tool relying on the scattering of light by repetitive structures. This technique provided not only line width information at smaller pitches, but also additional information such as height and profile of patterned structures. Being non-destructive and high throughput, it rapidly became a fab-critical tool for monitoring advanced processes.
Device innovations and the introduction of 193nm immersion lithography: the need for characterizing new materials and process-induced defects
From the early 2000’s to around 2011, we observed for the first time a slight deviation from the ‘perfect’ scaling path according to Moore's Law. To keep up with Moore’s Law and maintain performance improvement, strain was induced into Si conduction channels of 90nm MOSFET devices. This mobility booster was enabled by, e.g., adding SiGe stressors in source/drain regions. Also, from the 45nm node onwards, the traditional SiO2/poly-Si based gate stack was replaced by a high-k/metal gate stack to allow the gate to re-gain control over the channel, as such addressing short channel effects.
Introducing novel materials as an additional knob to boost performance presented a new challenge for metrology: the need to characterize these materials. And that’s when x-ray-based techniques entered the fab: in-line x-ray diffraction (XRD) for characterizing strained channels, and in-line x-ray photoelectron spectroscopy (XPS) for high-k/metal gates.
On the lithography side, an increase in resolution required by the continued dimensional scaling was provided by ArF-based lithography systems, using light at smaller wavelength (193nm) compared to KrF-based systems during exposure in the scanner. These 193nm ‘dry’ lithography systems were followed by 193nm immersion lithography scanners to enable even smaller pitches. Here, the optical trick of replacing the air between lens and wafer with water allowed a 45% increase in numerical aperture (NA) – a metric that controls the amount of light (more precisely, the number of diffraction orders captured by the lens) that is used to form the image. But the resulting leap in resolution came with a downside: the presence of water created so-called bubble defects that posed additional challenges for inspection tools: the need to detect small and process induced defects over the full wafer.
193nm immersion lithography triggered the first use of broadband plasma tools within the fab, tools that operate with laser-pumped plasma light sources. These tools are still in use today for characterizing the most advanced device structures and for back-end-of-line inspection.
The FinFET era and the emergence of multi-patterning: an accelerated overlay roadmap, the EPE metric, first 3D metrology techniques
The third period can be referred to as the FinFET era, marking the first significant architectural shift in transistor device history. In a FinFET, the conduction channel between source and drain terminals is in the form of a three-dimensional fin, and the gate wraps around this channel – providing control from three sides of the channel. This multi-gate structure was introduced in the 22nm node to further reduce short-channel effects, which continued to degrade transistor performance at reduced gate length.
The advent of 3D device technology in its early stages heralded the beginning of the 3D metrology era. Scatterometry, which was introduced in the first period, turned out to be fully effective in the 3D space. Also, the metrology community started considering hybrid metrology: combining different techniques – such as optical critical dimension (OCD) metrology and CD-SEM – to extract more information or in a more accurate way.
In the same period, lithography and patterning went through an historic change as well: for the first time, double-patterning techniques were being used to extend 193nm lithography in anticipation of extreme ultraviolet (EUV) lithography being ready for mass production. With double (or multi-) patterning, a chip pattern is split into two (or more) ‘simpler’ masks. This allows printing smaller features but increases the complexity and cost of the chip manufacturing process.
More specifically, double patterning significantly increases the requirements for overlay between the two successively patterned layers, reducing the budget for overlay errors. That’s when imec and the metrology community introduced the edge placement error (EPE) metric, describing how the placement of the various structures deviates from the intended design. Metrologists had to find a way to measure all the parameters that enter the EPE equation. It also urged the need for improved process control for overlay and brought in new algorithms for CD-SEM – as to characterize the two different CD populations that were created by the two separate lithography and patterning steps.
The EUV era: metrology solutions to address stochastic effects
In 2019, the semiconductor industry used Low NA (0.33NA) EUV lithography and patterning for the first time in the mass production of logic chips of the 7nm node [2,3]. Its introduction came with its own set of challenges. Using EUV light of 13.5nm during exposure in the lithography scanner significantly reduces the number of photons hitting the wafer, compared to 193nm lithography. And this induces random effects on the printed structures, referred to as the stochastic effects of EUV lithography. These stochastic effects can be grouped into two categories, each of which necessitated innovations in metrology – guided by pioneering work from imec and its partners in understanding these effects [4].
Figure 2 – (Top) The reduced number of photons during EUV exposure causes stochastics effects such as (bottom) increased line roughness (as presented at 2026 SPIE AL+P [1]).
First, stochastic effects have a severe impact on the line roughness, translating into increased line edge roughness and top line roughness. Measuring line edge roughness has been addressed by improved CD-SEM techniques, optimized to measure so-called unbiased roughness [5]: by eliminating noise coming from the SEM itself, these measurements could provide a better estimate of the true feature roughness. Characterizing top line roughness, on the other hand, was facilitated by AFM.
A second aspect is the presence of stochastic defects, failures that manifest as random line bridges or breaks, or as closing or bridging contact holes [4]. This called for techniques that can both detect extremely small defects (of the order of 10nm and even less) and map a large area of the wafer – two needs that can hardly be met with only one metrology technique. Optical inspection techniques allow to map a large area but are being challenged by the small scale of the defect. E-beam, on the other hand, is a very powerful technique for detecting small defects, but it lacks the throughput for mapping a full wafer. The answer is in combining both techniques to characterize EUV printed defects and define what is called the failure-free process window for EUV lithography.
The future metrology and inspection roadmap: addressing both xy and z scaling, reducing metrology’s carbon footprint
Dimensional scaling remains an essential pillar in continuing the logic roadmap and unlocking the next wave of AI. Today, industry continues to use 0.33NA EUV lithography to print the critical layers of the most advanced nodes, i.e., 3nm and 2nm logic nodes. Meanwhile, imec and its ecosystem partners have made great strides in readying High NA (0.55NA) EUV lithography and patterning technologies to enable sub-2nm nodes, ensuring increased resolution, process simplification (by reducing the need for multi-patterning), and design flexibility (through the introduction of 1.5D, 2D and curvilinear geometries) [2,6,7].
Innovations in patterning are complemented by even more disruptive innovations in device architectures and materials. Gate-all-around nanosheet transistors have recently been introduced in commercial compute systems and will most likely be succeeded by complementary FETs (CFETs) from the A7 node onwards – according to imec’s logic roadmap [8]. Device architectures will as such increasingly move towards the 3rd dimension. This trend is also defining the (future) memory landscape – with 3D NAND as the workhorse storage system and DRAM evolving towards 3D architectures. The 3rd dimension additionally enables new chip interconnect architectures – think about backside power delivery networks and backside contacting of bottom CFET devices. Overall, future compute systems will increasingly rely on 3D integration technologies, including die-to-wafer and wafer-to-wafer hybrid bonding technologies.
Grand challenges: different requirements for xy scaling and z scaling
All these future options translate into grand challenges and opportunities for metrology and inspection. In terms of ‘xy scaling’ – enabled by advanced lithography and patterning – challenges include the need for increased xy resolution, the characterization of curvilinear shapes, the ability to detect tiny defects on large wafer areas, and the need for vertical sensitivity to characterize structures with varying profiles. ‘Z scaling’, on the other hand – enabled by 3D devices and 3D integration technologies – involves different grand challenges: it’s about characterizing multilayers and high aspect ratio structures, ‘seeing through’ opaque materials, dealing with topographies at different scales, and measuring edges and backsides of wafers.
Imec’s roadmap for metrology and inspection
These challenges form the basis of imec's roadmap for metrology, inspection, and characterization, which details when the technologies needed to address these challenges, should be ready and mature for industry.
Figure 3: Imec’s metrology, inspection and characterization roadmap in support of advanced lithography, logic, memory and packaging technologies (as presented at 2026 SPIE AL+P [1]).
Two important evolutions will help shape that roadmap: (1) innovations in hardware, and (2) the increasing use of data. First, developments are ongoing to extend hardware for improved sensitivity: e-beam metrology with electrons at higher electron Volt to improve resolution, optical metrology with photons at smaller wavelengths to detect tiny defects, and x-rays to probe deeper into silicon. At the same time, multiple innovations are being explored to further boost throughput while keeping ultimate resolution and defect sensitivity: the potential of both multi-head atomic force microscopy and multi e-beam inspection has recently been demonstrated for detecting tiny defects at very high throughput [1].
Second, gaps are being filled by making greater use of data and algorithms to boost metrology performance. A first example is the use of AI-based algorithms to de-noise incoming measurement data such as e-beam images. Another example is referred to as virtual metrology (or ‘measure-less’ metrology): data measured with a physical metrology tool is complemented and extended with data coming from a virtual metrology model. The latter leverages the conditions of a process tool (e.g., power, temperature, flow rate...) – as measured by sensors that are attached to the tool – to predict the outcome of a metrology measurement.
Figure 4 – The principle of virtual metrology (as presented at 2026 SPIE AL+P [1]).
Reducing the carbon footprint
Present and future developments also focus on reducing the carbon footprint of metrology and inspection as much as possible. Imec used its imec.netzero virtual fab model to quantify the share of metrology in the environmental impact of manufacturing the 28nm logic node [9]. Compared to other process areas (such as etch and deposition), the contribution of metrology to overall emissions was found to be relatively small. Nevertheless, measuring accurately at the right process steps is key in improving process yield and reducing waste, highlighting the role metrology should play in reducing the environmental impact of chip manufacturing.
Figure 5 – N28 total emissions by process area, generated by the imec.netzero v6.1.57 web app (as presented at 2026 SPIE AL+P [1]).
Conclusion
Wrapping up 40 years of metrology shows how new metrology and inspection techniques have emerged, thereby diversifying the metrology toolbox to address the continued dimensional scaling and increase in process complexity. Imec and its metrology partners played an important role in pioneering new technologies in support of the logic technology roadmap.
The (merely optical) techniques of the early days have, however, not disappeared: in an evolved form, they are still an integral part of state-of-the-art semiconductor process verification and control. The future technology roadmap – with further advancements in xy scaling and increasing use of z scaling – will further diversify this toolbox, complemented with innovations in existing hardware and an increase in the use of data.
Figure 6 – Metrology and inspection techniques adopted over the last 40 years (as presented at 2026 SPIE AL+P [1]).
The next 40 years continue to bring exciting opportunities to the metrology community. But it also raises questions, for example, about the increased level of automation and role of AI in metrology: how will we guarantee the physical meaning of measured data? What will be the role of metrology experts? Which new sensors will we need to attach to our metrology tools to further boost virtual metrology? And are there more lab techniques to be deployed in the fabs?
At imec, we continue expanding our metrology ecosystem to help monitor and characterize advanced technology platforms for logic, memory, lithography and packaging. This metrology ecosystem will also support the EU funded NanoIC pilot line that is hosted by imec, as such playing a critical role in realizing the European Chips Act’s ambitions for enabling sub-2nm logic technology nodes.
This article was originally published in Electronics Weekly.
Want to know more?
[1] ‘40 Years of semiconductor metrology: connecting the past to the future,’ A.-L. Charley et al., 2026 SPIE Advanced Lithography and Patterning, Keynote presentation at the Metrology, Inspection, and Process Control conference;
[2] ‘High-NA EUV lithography: the next major step forward,’ D. De Simone et al., imec Reading Room 2021;
[3] ‘EUVL is being inserted in manufacturing in 2019: What are the mask related challenges remaining?’, Proceedings Volume 11177, 35th European Mask and Lithography Conference (EMLC 2019); 111770A (2019) https://doi.org/10.1117/12.2535821
[4] ‘Sailing along the stochastic cliffs,’ P. De Bisschop et al., imec Reading Room 2019;
[5] ‘The need for LWR metrology standardization: the imec roughness protocol,’ Proceedings Volume 10585, Metrology, Inspection, and Process Control for Microlithography XXXII; 105850D (2018) https://doi.org/10.1117/12.2294617
[6] ‘Imec demonstrates readiness of the High-NA EUV patterning ecosystem,’ imec press release 2024
[7] ‘The case for High NA EUV: unlocking the next era of chip manufacturing,’ G. Vandenberghe, imec Reading Room 2026;
[8] ‘Performance boosters to scale monolithic CFET across multiple logic technology nodes,’ S. Yang et al., imec Reading Room 2026;
