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<h2 id="bl0_part0">General information</h2><ul><li><a href="/imec-icon-general-infosession">imec.icon -&nbsp;Information session</a></li><li><a href="/imec-icon-manual">imec.icon - manual</a></li></ul>

<h2 id="bl1_part0">Contracts</h2><ul><li><a class="file file--mime-application-vnd-openxmlformats-officedocument-wordprocessingml-document file--x-office-document" href="/sites/default/files/inline-files/20250324_imec.icon%20Samenwerkingsovereenkomst.docx" data-entity-uuid="268b3763-f1b5-49e6-a432-8aa7af4523cc" data-entity-type="file" filename="20220916_imec.icon 2022 Samenwerkingsovereenkomst update.docx">ICON Collaboration agreement</a></li></ul>

Want to know more about imec.icon?

The imec.icon research program is our successful formula for demand-driven, cooperative research on hardware-, software- and combined hardware/software innovati

Research is what defines us. It is our roots. Whether you seek specific support or work with multiple partners, we accelerate your progress.  

We offer you both R&amp;D solutions to create new technologies as well as innovation services applicable to both products and services. Your project can be big 

What we offer

Research

imec.icon

Research Portfolio

Discover how the imec.icon program can help you kick-start your cooperative research project in the digital technologies and nano electronics.  

imec.icon Open Call

imec.icon - Start a new abstract

MyProject video tutorials

Pieter Simoens

Vision

Real transformation will come with agentic and physical AI: systems that don’t just think and generate, but act in the real world.But before these next-gen systems can become widespread, there’s a towering challenge: the hardware has to keep up.

Agentic and physical AI will change everything  

Validating sustainability strategies with real-fab solutions.

Emily Gallagher

Validating sustainability strategies with real-fab solutions

Featured in the media

The semiconductor industry is experiencing rapid growth and contributes to increasing environmental impacts.In this article, we simulate scenarios and identify semiconductor processes with the highest impact in emissions, chemical use and water consumption.We explore strategies to mitigate these impacts through process optimization and material efficiency.Real-fab examples from lithography, etch, and wet processes demonstrate how climate-aware optimization strategies can significantly reduce the overall environmental footprint of the semiconductor industry.

How can we reduce environmental impact in chip manufacturing?

A path to high-density front- and backside wafer connectivity

Zsolt Tokei

Eric Beyne

Geert Hellings

Julien Ryckaert

Advances in wafer-to-wafer hybrid bonding and backside technologies take CMOS 2.0 from concept to reality, offering more options for compute system scaling

Page-turner

At VLSI 2025, imec researchers demonstrated the feasibility of expanding the roadmap for wafer-to-wafer hybrid bonding toward 250nm interconnect pitch.They also showed highly dense connections at the wafer’s backside through the fabrication of extremely small through-dielectric vias, at 120nm pitch.The ability to make such highly dense connections on both sides of the wafer presents a milestone for developing CMOS 2.0-based compute system architectures that rely on the stacking of functional tiers within a system-on-chip.CMOS 2.0-based systems will additionally make use of backside interconnects including power delivery networks (BSPDNs), the benefits of which could be demonstrated for the first time in switched-domain designs – relevant for mobile use cases.

Testimonial

Where innovation meets well-being: The Workplace Vitality Hub.

From curiosity to impact: A PhD journey at imec

The agreement marks the start of a new five-year phase in their long-standing alliance.

Jade Liu

Imec and Tokyo Electron extend partnership to accelerate the development of beyond-2nm nodes  

Improved contact resistance and RF output are key toward mobile-compatible E-mode GaN-on-Si transistors.

Record-breaking RF GaN-on-Si transistor performance for high-efficiency 6G power amplifiers

Improved contact resistance and RF output key toward mobile-compatible E-mode GaN-on-Si transistors

Imec achieves record-breaking RF GaN-on-Si transistor performance for high-efficiency 6G power amplifiers 

Improved manufacturability and performance compared to the earlier inner wall forksheet.

Outer wall forksheet to bridge nanosheet and CFET device architectures

Lynn Verschueren

Improved manufacturability and performance compared to the earlier inner wall forksheet

Research update

In 2017, imec introduced the forksheet as a scalable device architecture to extend the gate-all-around (GAA) nanosheet-based logic roadmap in the least disruptive way possible.Concerns about manufacturability gave way to an improved forksheet architecture: the outer wall forksheet.At VLSI 2025, imec showed simulations highlighting the benefits of the outer wall forksheet compared to the earlier inner wall design: easier fabrication, superior gate control, connected n-p gates, and the ability to achieve full channel stress.The outer wall forksheet architecture is an attractive option for the industry to extend the nanosheet era to the A10 node, in anticipation of the CFET going into mass production.

Outer wall forksheet to bridge nanosheet and CFET device architectures in the logic technology roadmap

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